1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a technique for preventing defects associated with etching.
2. Description of the Background Art
Conventionally, semiconductor devices having a plurality of MOS configurations have been manufactured (e.g. Japanese Patent Application Laid-Open No 2007-19396). It is to be noted that in the present specification, the term MOS is broadly applied to a transistor using a material other than an oxide as a gate insulating film.
In the conventional semiconductor device manufacturing method, there have been two problems as described below.
The first problem is as follows. As shown in FIGS. 5 to 6 of Japanese Patent Application Laid-Open No 2007-19396, a metal layer 64 on the top of a P-type well 32 is selectively removed, and at this time, a problem occurs in which a gate insulating film 5 on the P-type well 32 is damaged and a leak current of the gate insulating film 5 thus increases. This is because part of the metal layer 64 and the gate insulating film 5 are reacted with each other to form an interfacial layer during the time between deposition and removal of the metal layer 64 and this interfacial layer is also removed in the removal of the metal layer 64.
The second problem is as follows. As shown in FIGS. 7 and 8 of Japanese Patent Application Laid-Open No 2007-19396, although simultaneous formation of a plurality of gate electrodes having different configurations is necessary, after etching of a polycrystal silicon layer 63, the metal layer 64 is exposed to the substrate surface in a PMOS and the gate insulating film 5 is exposed to the surface in an NMOS. In this state, for etching only the metal layer 64 without occurrence of penetration of the gate insulating film 5, the etching needs to be performed on condition of a large etching selection ratio of the metal to the gate insulating film. However, when the etching is performed with a large etching selection ratio of the metal to the gate insulating film, a side wall of the metal layer 64 cannot help but be formed into taper shape. Hence the film thickness of the insulating film, at the time of insulating film formation, becomes smaller at the lower end of the metal layer 64 having been formed into taper shape, thereby to cause deterioration in film-coating properties. Further, a problem occurs such as a problem in which injection into the transistor is affected by the taper of the metal layer, thereby to cause deterioration in transistor properties.